vishay siliconix TN2404K/TN2404Kl/bs107kl document number: 72225 s12-1767-rev. c, 23-jul-12 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com n-channel 240 v (d-s) mosfet features ? low on-resistance: 4 ? ? secondary breakdown free: 260 v ? low power/voltage driven ? low input and output leakage ? excellent thermal stability ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ? high-voltage drivers: relays, solenoids, lamps, hammers, displays, transistors, etc. ? telephone mute switches, ringer circuits ? power supply, converters ? motor control benefits ? low offset voltage ? full-voltage operation ? easily driven without buffer ? low error voltage ? no high-temperature ?run-away? notes: a. pulse width limited by maximum junction temperature. b. surface mounted on an fr4 board. product summary part number v ds (v) r ds(on) ( ? ) v gs(th) (a) i d (a) q g (typ.) TN2404K 240 4 at v gs = 10 v 0.8 to 2 0.2 4.87 nc TN2404K, bs107kl 0.3 TN2404Kl device marking front view ?s? tn 2404kl xxyy ?s? = siliconix logo xxyy = date code bs107kl device marking front view ?s? bs 107kl xxyy ?s? = siliconix logo xxyy = date code to-226aa (to-92) top view s d g 1 2 3 to-92-18rm (to-18 lead form) top view d s g 1 2 3 TN2404K g s d top v iew 2 3 to-236 (sot-23) 1 marking code: k1ywl k1 = part number code for TN2404K y = year code w = week code l = lot traceability ordring information standard partnumber ordering part number option TN2404K TN2404K-t1-e3 lead (pb) free TN2404K-t1-ge3 lead (pb) free and halogen free TN2404Kl TN2404Kl-tr1-e3 with tape and reel spool option bs107kl bs107kl-tr1-e3 absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol TN2404K TN2404Kl/bs107kl symbol drain-source voltage v ds 240 v gate-source voltage v gs 20 continuous drain current (t j = 150 c) t a = 25 c i d 0.2 0.3 a t a = 70 c 0.16 0.25 pulsed drain current (t = 300 s) i dm 0.8 1.4 maximum power dissipation t a = 25 c p d 0.36 0.8 w t a = 70 c 0.23 0.51 thermal resistance junction-to-ambient r thja 350 b 156 c/w operating junction and storage temperature range t j , t stg - 55 to 150 c
www.vishay.com 2 document number: 72225 s12-1767-rev. c, 23-jul-12 vishay siliconix TN2404K/TN2404Kl/bs107kl this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com notes: a. pulse test; pulse width ? 300 s, duty cycle ? 2 % b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications (t a = 25 c, unless otherwise noted) parameter symbol test conditions limits min. typ. a max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 100 a 240 257 v gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 0.8 1.65 2 gate-source leakage i gss v ds = 0 v, v gs = 20 v 100 na zero gate voltage drain current i dss v ds = 192 v, v gs = 0 v 1 a v ds = 192 v, v gs = 0 v, t j = 55 c 10 on-state drain current a i d(on) v ds ?? 10 v, v gs = 10 v 0.8 a v ds ?? 10 v, v gs = 4.5 v 0.5 drain-source on-state resistance a r ds(on) v gs ?? 10 v, i d = 0.3 a 2.2 4 ? v gs ?? 4.5 v, i d = 0.2 a 2.3 4 v gs ?? 2.5 v, i d = 0.1 a 2.4 6 forward transconductance a g fs v ds = 10 v, i d = 0.3 a 1.6 s diode forward voltage v sd v gs = 0 v, i s = 0.3 a 0.8 1.2 v dynamic b total gate charge q g v ds = 192 v, v gs = 10 v, i d = 0.5 a 4.87 8 nc gate-source charge q gs 0.56 gate-drain charge q gd 1.53 tu r n - o n d e l ay t i m e t d(on) v dd = 60 v, r l = 200 ? i d ? 0.3 a, v gen = 10 v, r g = 25 ? 510 ns rise time t r 12 20 turn-off delay time t d(off) 35 60 fall time t f 16 25
document number: 72225 s12-1767-rev. c, 23-jul-12 www.vishay.com 3 vishay siliconix TN2404K/TN2404Kl/bs107kl this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) output characteristics on-resistance vs. drain current gate charge 0.0 0.3 0.6 0.9 1.2 1.5 1. 8 012345 v gs = 10 thr u 3 v v ds ? drain-to-so u rce v oltage ( v ) ? drain c u rrent (a) i d 2 v 2.5 v ? on-resistance ( r ds(on) ) 0 1 2 3 4 5 0.0 0.2 0.4 0.6 0. 8 1.0 1.2 i d ? drain c u rrent (a) v gs = 10 v v gs = 4.5 v 0 2 4 6 8 10 012345 v ds = 192 v i d = 0.5 a ? gate-to-so u rce v oltage ( v ) q g ? total gate charge (nc) v gs transfer characteristics capacitance on-resistance vs. junction temperature 0.0 0.2 0.4 0.6 0. 8 1.0 1.2 1.4 0123456 t c = ?55 c 125 c 25 c v gs ? gate-to-so u rce v oltage ( v ) ? drain c u rrent (a) i d 0 50 100 150 200 250 300 0 1020304050 v ds ? drain-to-so u rce v oltage ( v ) c rss c oss c iss c ? capacitance (pf) 0.4 0.6 0. 8 1.0 1.2 1.4 1.6 1. 8 2.0 2.2 ?50 ?25 0 25 50 75 100 125 150 v gs = 4.5 v i d = 0.2 a t j ? j u nction temperat u re ( c) v gs = 10 v i d = 0.3 a r ds(on) ? on-resiistance ( n ormalized)
www.vishay.com 4 document number: 72225 s12-1767-rev. c, 23-jul-12 vishay siliconix TN2404K/TN2404Kl/bs107kl this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) source-drain diode forward voltage 0.0 0.2 0.4 0.6 0. 8 1.0 1.2 1.4 t j = 150 c 10 0.001 v sd ?) v ( e g a t l o v n i a r d - o t - e c r u o s ? so u rce c u rrent (a) i s t j = 25 c 1 0.1 0.01 t j = ?55 c on-resistance vs. gate-to-source voltage 0 1 2 3 4 5 6 7 8 0246 8 10 ? on-resistance ( r ds(on) ) v gs ? gate-to-so u rce v oltage ( v ) i d = 50 ma i d = 10 ma i d = 100 ma threshold voltage ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 ?0.0 0.1 0.2 0.3 ?50 ?25 0 25 50 75 100 125 150 v ariance ( v ) v gs(th) t j ? temperat u re (c) i d = 250 a
document number: 72225 s12-1767-rev. c, 23-jul-12 www.vishay.com 5 vishay siliconix TN2404K/TN2404Kl/bs107kl this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72225 . normalized thermal transient impedance, junction-to-ambient (to-236, TN2404K only) 10 ?3 10 ?2 0 0 6 0 1 1 10 ?1 10 ?4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 s qu are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1. d u ty cycle, d = 2. per unit base = r thja =350 c/ w 3. t jm ? t a = p dm z thja (t) t 1 t 2 t 1 t 2 n otes: 4. s u rface mo u nted p dm normalized thermal transient impedance, junction-to-ambient (to-226aa, TN2404Kl and to-92-18rm, bs107kl only) 10 k 1 0.01 0.1 0 0 1 1 1 . 0 k 1 0 1 d u ty cycle = 0.5 0.2 0.1 0.05 0.02 single p u lse 0.01 n ormalized effecti v e transient thermal impedance t 1 ? s qu are w a v e p u lse d u ration (s) 1. d u ty cycle, d = 2. per unit base = r thja = 156 c/ w 3. t jm ? t a = p dm z thja (t) t 1 t 2 t 1 n otes: p dm t 2
vishay siliconix package information document number: 71196 09-jul-01 www.vishay.com 1 sot-23 (to-236): 3-lead b e e 1 1 3 2 s e e 1 d a 2 a a 1 c s e a ting pl a ne 0.10 mm 0.004" c c l 1 l q g au ge pl a ne s e a ting pl a ne 0.25 mm dim millimeters inches min max min max a 0.89 1.12 0.0 3 5 0.044 a 1 0.01 0.10 0.0004 0.004 a 2 0.88 1.02 0.0 3 46 0.040 b 0. 3 5 0.50 0.014 0.020 c 0.085 0.18 0.00 3 0.007 d 2.80 3 .04 0.110 0.120 e 2.10 2.64 0.08 3 0.104 e 1 1.20 1.40 0.047 0.055 e 0.95 bsc 0.0 3 74 ref e 1 1.90 bsc 0.0748 ref l 0.40 0.60 0.016 0.024 l 1 0.64 ref 0.025 ref s 0.50 ref 0.020 ref q 3 8 3 8 ecn: s-0 3 946-rev. k, 09-jul-01 dwg: 5479
an807 vishay siliconix document number: 70739 26-nov-03 www.vishay.com 1 mounting little foot sot-23 power mosfets wharton mcdaniel surface-mounted little foot power mosfets use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. see application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfet s, ( http://www.vishay.com/doc?72286 ), for the basis of the pad design for a littl e foot sot-23 power mosfet footprint . in converting this footprint to the pad set for a power device, designers must make tw o connections: an electrical connection and a thermal connection, to draw heat away from the package. the electrical connections for the sot-23 are very simple. pin 1 is the gate, pin 2 is the source, and pin 3 is the drain. as in the other little foot packages, the drai n pin serves the additional function of providing the thermal connection from the package to the pc board. the total cross section of a copper trace connected to the drain may be adequate to carry the current required for the application, but it may be inadequate thermally. also, heat spreads in a circular fashion from the heat source. in this case the drain pin is the heat source when looking at heat spread on the pc board. figure 1 shows the footprint with copper spreading for the sot-23 package. this pattern shows the starting point for utilizing the board area available for the heat spreading copper. to create this pattern, a plane of copper over lies the drain pin and provides planar copper to draw heat from the drain lead and start the process of spreading the heat so it can be dissipated into the ambient air. this pattern uses all the available area underneath the body for this purpose. figure 1. footprint with copper spreading 0.114 2.9 0.059 1.5 0.0394 1.0 0.037 0.95 0.150 3.8 0.081 2.05 since surface-mounted packages are small, and reflow soldering is the most common way in whic h these are affixed to the pc board, ?thermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum power trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low-impedance path for heat to move away from the device.
application note 826 vishay siliconix document number: 72609 www.vishay.com revision: 21-jan-08 25 application note recommended minimum pads for sot-23 0.106 (2.692) recommended mi nimum pads dimensions in inches/(mm) 0.022 (0.559) 0.049 (1.245) 0.029 (0.724) 0.037 (0.950) 0.053 (1.341) 0.097 (2.459) return to index return to index
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